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上传的源码:
 1. vspi.rar,SPI串口的内核实现verilog语言和VHDL语言,6KB,下载 0

近期下载的代码:
 1. hdl-master.zip,AD9361的ip核,已经调试通过,在vivado上可以运行通。AD9361是一个双通道的便捷收发器,通常用于3G/4G基站。,1294KB,下载 105
 2. V2.tar.gz,SDIO slave, written in verilog, does not support SPI mode.,9KB,下载 21
 3. sd_card_controller_latest.tar.gz,The SD Card Controller IP Core is MMC/SD communication controller designed to be used in a System-on-Chip. The IP core provides a simple interface for CPU. The communication between the MMC/SD card controller and MMC/SD card is performed according to the MMC/SD protocol.,2236KB,下载 8
 4. ds768_axi_interconnect.rar,XILINX FPGA AXI总线互联IP datasheet, 用该IP可构建高速片上系统。内容包括了IP配置的说明等,534KB,下载 45
 5. MDIO.zip,网络PHY88E1111的 寄存器 通讯协议的 verilog描述 能实现 lookback 能读出PHY的资料,1KB,下载 163
 6. EMAC6.zip,verilog实现的FPGA三态以太网链路层通信代码,里面有状态机,并按各个模块的功能分了文件夹,还有说明文档,自定义帧的产生和接收,开发环境为Xilinx ISE,测试无误。,3518KB,下载 32
 7. 88E1111_full.rar,88E1111 千兆phy完整资料,如果做千兆应用可以看着个资料。 非常详细,1202KB,下载 395
 8. sdcard_mass_storage_controller.tar.gz,The "sd card controller" is a Secure Digital Card Host Controller, which main focus is to provide fast and simple interface to SD/SDHC cards. One of the main goal with this project is that the controller should be usable as a system disk contain a file system. Therefore the core has been developed with features a system with operative system will benefit from. The design also include a simplified model of a SD-card to test against. ,2233KB,下载 9
 9. sdModel.rar,SD Card的verilog模拟模型,可以配合开发SD Controller使用,5KB,下载 50
 10. SD_Controller_Verilog.rar,该程序包是SD卡/MMC卡控制器SDC的verilog语言包,它包括以下4部分:RTL源代码,测试平台,软件仿真文件,说明文件。,1621KB,下载 122
 11. LIP1742CORE_sdio_rx_fsm.rar,Verilog SDIO RX FSM module,254KB,下载 21
 12. LIP1401CORE_IO_LVDS.rar,IO LVDS VHDL & Verilog code,35KB,下载 38
 13. sdcard_mass_storage_controller_latest..tar.gz,SD卡控制器,适合硬件工程师在FPGA内部实现SD 控制器,2234KB,下载 62
 14. LIP4210CORE_SDIO.rar,SDIO Verilog Sourcw code,4522KB,下载 82
 15. altera_up_avalon_sd_card_interface_91.rar,修改后的Altera大学计划IP Core,可用于QII9.1及9.1SP1,312KB,下载 38
 16. SDCard_Controller.rar,SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口,方便与其他IP连接使用。 ,24KB,下载 217
 17. SD_Host_Model_513_02.zip,可做SD的simulation model,3739KB,下载 131
 18. FPGA-SD-COMMUNICATION.rar,基于QUARTUSII软件 实现FPGA(ATERA CYCLONE II系列)与SD卡SD模式通信 所用语言位verilog HDL,4946KB,下载 467
 19. Ethernet_verilog_ip_core.rar,Ethernet(以太网)verilog ip core用verilogHDL语言写的以太网软核,对学习verilog语言和以太网有很大帮助。,882KB,下载 576
 20. sd_code.rar,SD卡开发源程序,可根据用户实际硬件修改,19KB,下载 154

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